部件型号 | 厂商 | 描述 |
---|---|---|
EF-DI-CAN-XC-SITE |
xilinx | The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gatewaysand body control unitsand automotive test equipm |
EF-DI-RSD-SITE |
xilinx | Reed-Solomon Encoder and Decoder are commonly used in data transmission and storage applicationsand such as broadcast equipmentand wireless LANsand cable modems |
EF-DI-VLYNQ-SITE |
xilinx | The VLYNQ core is comprised of logic dedicated to transmitting transactions onto the serial Tx lines and logic dedicated to receiving transactions from the seri |
EF-DI-INTERLEAV-SITE |
xilinx | The Interleaver/De-interleaver LogiCORE module is a high-speedand compact design that is fully synchronousand using a single clock. It's parameterizable feature |
EF-DI-RSE-SITE |
xilinx | REED SOLOMON ENCODER IMPLEMENTS MANY DIFFERENT REED SOLOMON CODING STANDARDSThe Reed-Solomon Encoder LogiCORE module is a high speedand compact design that impl |
EF-DI-VITERBI-SITE |
xilinx | Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception. Compatible with many common standards. |
DO-DI-PCI32-IP |
xilinx | 32-BIT INITIATOR/TARGET V3 AND V4 FOR PCI |
DO-DI-PCI64-IP |
xilinx | V3 AND V4 64-BIT VIRTEX AND SPARTAN AND VIRTEX PRODUCT LOUNGE FOR PCI CORES |
DO-DI-POSL3MC |
xilinx | LogiCORE POS-PHY L3 Link Layer Interface, Multi - Channel |
DO-DI-VITERBI |
xilinx | LogiCORE Viterbi Decoder |
EF-DI-PCI-AL-SITE |
xilinx | The PCI-X Interface is a pre implemented and fully tested module for Xilinx FPGAs. This significantly reduces engineering time required to implement the PCI-X portion of your design. |
EF-DI-PCI32-SP-PROJ |
xilinx | The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-PCI64-IP-SITE |
xilinx | The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-USB2-DEVICE-SITE |
xilinx | The USB 2.0 protocol multiplexes many devices over a singleand half-duplex serial bus. The bus runs at 480 Mbps or at 12 Mbps and is designed to be plug-and-play. |
EF-DI-CHDEC-LTE-SITE |
xilinx | The 3GPP LTE Channel Decoder provides a high-performanceand optimized decode function for the Uplink Shared Channel (UL-SCH)and as defined in 3GPP TS 26.212 v9.3.0. |
EF-DI-CPRI-SITE |
xilinx | Logicore IP Is A High-Performance, Low Cost Flexible Solution |
EF-DI-CTC-80216E-DEC-SITE |
xilinx | The IEEE 802.16e CTC Decoder Core performs iterative decoding of channel data that has been encoded as described in Section 8.4.9 of the IEEE Std 802.16e specification. |
EF-DI-OBSAI-SITE |
xilinx | HIGH PERFORMANCE IP CORE IMPLEMENTS AN OBSAI RP3 INTERFACE |
EF-DI-PCI32-IP-SITE |
xilinx | The Initiator and Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. |
EF-DI-RIO-PHY-SITE |
xilinx | Logicore IP Serial Rapidio Endpoint |
EF-DI-TCCDEC-SITE |
xilinx | The TCC decoder is used in conjunction with a TCC encoder to provide a reliableand extremely effective way to transmit data over noisy data channels. |
EF-DI-10-100-EMAC-SITE |
xilinx | The EMAC Interface design is a soft intellectual property (IP) core designed for implementation in several Xilinx FPGAs. |
EF-DI-IMG-STATS-SITE |
xilinx | The Image Statistics LogiCORE IP implements the computationally-intensive metering functionality common in digital camerasand camcorders and imaging devices. |
EF-DI-PCIX64-VE-SITE |
xilinx | The PCI-X Interface is a pre implemented and fully tested module for Xilinx FPGAs. This significantly reduces engineering time required to implement the PCI-X portion of your design. |
EF-DI-IMG-MA-NOISE-SITE |
xilinx | The Motion Adaptive LogiCORE IP allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed. |
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